NFBEN=0, OBDFLT=0, OBDF=00, OBE=0, OBEOCD=0, PSYE=0, OAHLD=0, NFCSA=00, NFCSB=00, OBHLD=0, OAEOCD=0, OAE=0, CPSCIR=0, OADF=00, NFAEN=0, OADFLT=0
General PWM Timer I/O Control Register
| GTIOA | GTIOCnA Pin Function Select |
| CPSCIR | Complementary PWM Mode Initial Output at Synchronous Clear Disable 0 (0): Output the initial value set by the GTIOR.GTIOA and GTIOB bits when synchronous clear occurs in Trough section of complementary PWM mode 1 (1): Disable output the initial value |
| OADFLT | GTIOCnA Pin Output Value Setting at the Count Stop 0 (0): The GTIOCnA pin outputs low when counting stops 1 (1): The GTIOCnA pin outputs high when counting stops |
| OAHLD | GTIOCnA Pin Output Setting at the Start/Stop Count 0 (0): The GTIOCnA pin output level at the start or stop of counting depends on the register setting 1 (1): The GTIOCnA pin output level is retained at the start or stop of counting |
| OAE | GTIOCnA Pin Output Enable 0 (0): Output is disabled 1 (1): Output is enabled |
| OADF | GTIOCnA Pin Disable Value Setting 0 (00): None of the below options are specified 1 (01): GTIOCnA pin is set to Hi-Z in response to controlling the output negation 2 (10): GTIOCnA pin is set to 0 in response to controlling the output negation 3 (11): GTIOCnA pin is set to 1 in response to controlling the output negation |
| OAEOCD | GTCCRA Compare Match Cycle End Output Invalidate 0 (0): Validate GTIOA[3:2] setting 1 (1): Invalidate GTIOA[3:2] setting (GTIOCnA pin output is retained) |
| PSYE | PWM Synchronous output Enable 0 (0): Disable GTCPPOm pin output 1 (1): Enable GTCPPOm pin output |
| NFAEN | Noise Filter A Enable 0 (0): The noise filter for the GTIOCnA pin is disabled 1 (1): The noise filter for the GTIOCnA pin is enabled |
| NFCSA | Noise Filter A Sampling Clock Select 0 (00): GTCLK/1 1 (01): GTCLK/4 2 (10): GTCLK/16 3 (11): GTCLK/64 |
| GTIOB | GTIOCnB Pin Function Select |
| OBDFLT | GTIOCnB Pin Output Value Setting at the Count Stop 0 (0): The GTIOCnB pin outputs low when counting stops 1 (1): The GTIOCnB pin outputs high when counting stops |
| OBHLD | GTIOCnB Pin Output Setting at the Start/Stop Count 0 (0): The GTIOCnB pin output level at the start/stop of counting depends on the register setting 1 (1): The GTIOCnB pin output level is retained at the start/stop of counting |
| OBE | GTIOCnB Pin Output Enable 0 (0): Output is disabled 1 (1): Output is enabled |
| OBDF | GTIOCnB Pin Disable Value Setting 0 (00): None of the below options are specified 1 (01): GTIOCnB pin is set to Hi-Z in response to controlling the output negation 2 (10): GTIOCnB pin is set to 0 in response to controlling the output negation 3 (11): GTIOCnB pin is set to 1 in response to controlling the output negation |
| OBEOCD | GTCCRB Compare Match Cycle End Output Invalidate 0 (0): When Saw-wave PWM mode 1, validate GTIOB[3:2] setting When Saw-wave PWM mode 2, validate GTIOA[3:2] setting 1 (1): When Saw-wave PWM mode 1, invalidate GTIOB[3:2] setting (GTIOCnB pin output is retained) When Saw-wave PWM mode 2, invalidate GTIOA[3:2] setting (GTIOCnA pin output is retained) |
| NFBEN | Noise Filter B Enable 0 (0): The noise filter for the GTIOCnB pin is disabled 1 (1): The noise filter for the GTIOCnB pin is enabled |
| NFCSB | Noise Filter B Sampling Clock Select 0 (00): GTCLK/1 1 (01): GTCLK/4 2 (10): GTCLK/16 3 (11): GTCLK/64 |